In recent years, switching elements (IGBTs, MOSFETs, and JFETs) included in power conversion devices such as inverters and converters have become increasingly high in voltage resistance and speed. In this situation, research and development has been actively conducted on power conversion devices, for increasing the power of power conversion devices using switching elements with high voltage resistance, and for reducing the size of power conversion devices by achieving high-frequency operation thereof using switching elements with high speed.
In operation of switching elements of such a power conversion device, a pair of upper or lower arms are normally switched alternately with a predetermined break period (generally referred to as a dead time) therebetween to avoid simultaneous on conduction of the upper and lower arms causing short-circuiting. The higher the voltage applied to a switching element, or the higher the operation speed of a switching element, the larger the change rate of the voltage applied to the switching element (normally expressed by dv/dt) is. When the change rate is large, a charge current will flow from a main terminal to a control terminal via a parasitic capacitance C in the other switching element of the pair, changing the voltage of the control terminal in proportion to the value of the charge current. When such operation occurs, the voltage of the control terminal may possibly exceed the threshold voltage of the switching element. If the voltage of the control terminal changes and exceeds the threshold voltage during a predetermined break period, the upper and lower arms will conduct simultaneously causing short-circuiting, resulting in breaking of the switching element, and moreover failure of the power conversion device.
Referring to FIG. 4, a mechanism of malfunction of a lower arm 22u due to turn-on operation of an upper arm 21u will be described. Assume that the upper and lower arms 21u and 22u are in a break period during which they are both off (dead time). The break period is equal to or less than 1/20 of the switching frequency of an inverter, for example. In general, the switching frequency is 15 kHz or less for an inverter adapted to conversion of large power.
After the break period, when the upper arm 21u turns on, a DC voltage Vdc of a battery 1 is applied between the drain and source of the lower arm 22u. A parasitic capacitance 200 of the lower arm 22u is rapidly charged according to the switching speed of the upper arm 21u, causing flow of a current Ig via a lower-arm gate resistance 104u and a lower-arm arm-drive circuit 102u. With this flow of the current Ig, a potential difference corresponding to the value of the lower-arm gate resistance 104u occurs at both ends of the lower-arm gate resistance 104u. The potential difference occurring at both ends of the lower-arm gate resistance 104u, i.e., the gate-source potential difference Vgs of the lower arm 22u is expressed byVgs=Rg×Cgd×(dVdc/dt)where Cgd is the drain-gate parasitic capacitance of the lower arm 22u and Rg is the resistance of the lower-arm gate resistance 104u. 
That is, as the resistance Rg of the lower-arm gate resistance 104u that determines the switching speed of the lower arm 22u, the parasitic capacitance Cgd of the lower arm 21u, and the value of the switching time dVdc/dt of the upper arm 21u are larger, Vgs becomes larger, and the lower arm 22u is more likely to cause malfunction.
The resistance Rg of the lower-arm gate resistance 104u cannot be reduced arbitrarily because it is a value determining the switching speed of the lower arm 22u. The parasitic capacitance Cgd of the lower arm 21u cannot be changed arbitrarily, either, because it is determined by the internal structure of the lower arm 22u. If the switching time dVdc/dt of the upper arm 21u during its turn-on operation is reduced, the switching speed of the upper arm 21u will be reduced, resulting in increase in switching loss.
To avoid the above problems, conventionally, a negative bias voltage is applied to the control terminal of a switching element over the time period when the switching element is off, including a voltage change time when the voltage at the control terminal changes due to a charge current, if any, so that no short-circuited state occurs. With this application of a negative voltage, short-circuiting due to simultaneous conduction can be avoided. This technique is suggested in Patent Document 1, for example.
Patent Document 1 also discloses that, in the disclosed inverter, to turn off a switching element, a negative bias voltage is not output from a power supply, but can be applied with only circuits such as a capacitor and a diode, a FET, and the like. Therefore, constraints of the power supply voltage can be reduced, and moreover, heat dissipation of a drive circuit can be avoided.